1. Field of the Invention
The invention relates generally to flash memory devices and more particularly to very high-density, high-speed, low-voltage and low-power stacked-gate flash memory device and its memory arrays.
2. Description of Related Art
The flash memory devices are known to store charges in an isolated gate (known as the floating gate) by means of either Fowler-Nordheim tunneling or hot-carrier injection through a thin insulator layer from the semiconductor substrate and to remove or erase charges stored in an isolated gate by means of Fowler-Nordheim tunneling through a thin insulator layer to the semiconductor substrate or the control gate. Basically, the cell size must be scaled down for high-density mass storage applications and the device structure must be developed toward low-voltage, low-current and high-speed operation with high endurance and high retention.
A typical stacked-gate flash memory device in a conventional flash memory array is shown in FIG. 1, where FIG. 1A shows the schematic cross-sectional view in the channel-length direction; FIG. 1B shows the schematic cross-sectional view in the channel width direction; FIG. 1C shows the top-plan view of a NOR-type configuration. The stacked-gate flash memory device shown in FIG. 1A includes a p-type semiconductor substrate 100 and a p-well 101 formed in the p-type semiconductor substrate. A thin tunneling-oxide layer 102 is provided on the surface of a p-well 101 having a thickness of approximately 100 Angstroms. A polycrystalline-silicon layer 103 acted as the floating gate is provided on a thin tunneling-oxide layer 102 and an inter-gate dielectric layer 104 using the silicon oxide-silicon nitride-silicon oxide (ONO) structure separates the floating gate 103 and the control gate 105. The control gate 105 can be a heavily-doped polycrystalline-silicon or a heavily-doped polycrystalline-silicon layer capped by a silicide layer. The source diffusion regions 106 and the drain diffusion regions 107 are formed in a self-aligned manner. The source diffusion regions 106 can be the heavily-doped n+ regions and the drain diffusion regions 107 can be the double-diffused structure having the lightly-doped nxe2x88x92 regions in the heavily-doped n+ region to reduce the band-to-band tunneling effects during erase.
It is clearly seen from FIG. 1A that the gate length of a stacked-gate structure is mainly limited by the minimum feature size (xcex) of technology used and the minimum feature size (xcex) is mainly limited by the photo-lithographic technology. However, the spacing (xcexxe2x80x2) between devices is in general larger than the minimum feature size (xcex), i.e., xcexxe2x80x2=xcex+2xcex94xcexxe2x80x2, for contact implementation. Therefore, the effective length per cell is about 2xcex(1+xcex94xcexxe2x80x2/xcex) greater than 2xcex. Moreover, the applied source voltage with respect to the drain (in general grounded) for hot-electron generation during programming can be reduced only when the gate length xcex is reduced and the applied control-gate voltage for programming can be reduced by only increasing the coupling ratio of the floating gate. Similarly, the coupling ratio of the floating gate plays a major role on the reduction of applied voltage for erasing the stored charges in the floating gate to either the p-well or the control gate.
The coupling ratio of a stacked-gate flash memory device can be improved by the isolation structure in the channel-width direction. FIG. 1B shows a typical shallow-trench-isolation (STI) technique for high-density stacked-gate flash memory array in the channel-width direction, where the etched monocrystalline-silicon trenches in the p-well 101 are oxidized to form thin thermal silicon-oxide layers 108 before the filling silicon-oxide layers 109 are formed. The floating gate 103 is defined photolithographically to extend xcex94xcexxe2x80x3 over the isolation regions in order to increase the coupling ratio of the floating gate. Apparently, the width of isolation xcexxe2x80x3 must be equal to or larger than xcex+2xcex94xcexxe2x80x3, i.e., xcexxe2x80x3xe2x89xa7xcex+2xcexxe2x80x3, the effective width per cell is then about 2(xcex+xcex94xcexxe2x80x3). For NOR-type configuration, the effective area per cell is then about 4xcex2(1+xcex94xcexxe2x80x3/xcex) (1+xcex94xcexxe2x80x2/xcex), as shown in FIG. 1C. Moreover, the photolithographic misalignment tolerance of the floating gate may produce different coupling ratios from wafer to wafer and asymmetric device isolation phenomena. It is clearly visualized that the coupling ratio of the floating gate shown in FIG. 1B is increased by sacrificing the effective cell area. From the paper published by K. Imamiya et al., xe2x80x9cA 130-xcexcm2, 256-Mbit NAND Flash with Shallow Trench Isolation Technologyxe2x80x9d, IEEE Jour. of Solid-State Circuits, Vol. 34, NO. 11, pp. 1536-1541, Nov. 1999, the non-self-aligned floating gate is composed of two polycrystalline-silicon layers, xcex=0.25 xcexcm, xcex94xcexxe2x80x3=0.1xcex=0.025 xcexcm, xcex94xcexxe2x80x2=0.03375 xcexcm and apparently asymmetric xcex94xcexxe2x80x3 for memory cell due to photolithographic misalignment error can be seen from a photograph of their publication. If xcex94xcexxe2x80x3=0 for self-aligned floating gate, the effective area per cell can be reduced by 10% and the misalignment of the floating gate can be automatically eliminated.
There are several U.S. patents concerning the implementation of a self-aligned floating gate having higher coupling ratio. U.S. Pat. No. 6,140,182 described a silicon-nitride masking to remove the floating-gate polycrystalline-silicon layer over the isolation regions for both LOCOS and shallow trench isolations. There are two major disadvantages: one is the removal of pad-oxide over the active regions after forming the planarized isolation-oxides using shallow-trench-isolation; the other is the removals of the masking silicon-nitride layer over the polycrystalline-silicon layer and the polycrystalline-silicon layer over the isolation oxides. The removal of pad-oxide after forming the isolation oxides may cause the variations of the height of isolation oxides, which will change (reduce) the coupling ratio in certain errors. Besides, the active device surface and the upper comer will be etched if an anisotropic etching is used, resulting in poor surface for growing the thin tunneling-oxide layer; or both the bottom and upper comers of isolation-oxide edges will be etched if wet chemical is used, resulting in the etching holes at the bottom comers of the isolation oxides for over-etching and non-uniform thickness of the thin tunneling-oxide for under-etching. Similarly, the removals of the capped silicon-nitride layer and the polycrystalline-silicon layer over the isolation oxides may produce the errors for the height of extended side-wall floating gate. Moreover, the irregular shape of tips of etched polycrystalline-silicon floating gate may cause the stored-charge retention and disturb problems due to field emission. In addition, no channel stops are performed for shallow-trench-isolation to eliminate the surface leakage current. U.S. Pat. No. 5,770,501 used liquid-phase deposition (LPD) to form isolation-oxides within the slots of the patterned photoresist, as described by U.S. Pat. No. 5,516,721. It is quite apparent that the etched surface of the shallow trenches is impossible to grow the thermal oxides in order to eliminate the defects produced by trench etching; moreover, the height of LPD oxide is difficult to be controlled, which determines the coupling ratio of the self-aligned floating gate. The major disadvantages appeared in U.S. Pat. No. 5,516,721 was revised by U.S. Pat. No. 6,153,472 in which the polycrystalline-silicon spacers are formed on the sidewalls of the planarized filling oxides and the etched trench surface of shallow-trench-isolation and the sidewalls of etched major floating-gate polycrystalline-silicon layer are oxidized. It is clearly seen that the oxidized process may largely increase the thickness of the tunneling-oxide layer near the edges through the bird""s beak effects and the effective active width of so called flash memory devices will be reduced. Moreover, no channel stops are performed for shallow-trench-isolation.
From the above descriptions, the self-aligned floating gate is required in order to reduce the isolation area and higher coupling ratio of the self-aligned floating gate is important to increase the program and erase efficiency of applied control-gate voltage. Moreover, if the minimum feature size xcex can be removed from defining the gate length of stacked-gate flash memory device, the cell size and the applied source/drain voltage can be further reduced.
It is therefore an objective of this invention to provide a method of fabricating a scalable stacked-gate flash memory device having highly adjustable coupling ratio for high-density, high-speed, low-voltage and low-power mass storage applications to overcome the disadvantages of the prior arts.
The invention discloses in general a method of fabricating a scalable stacked-gate flash memory device and its high-density memory arrays using four different spacer techniques. The first spacer technique of the present invention is used to form the buffer-oxide spacers for implanting the channel stops of shallow-trench-isolation and oxidizing the etched surface of shallow trenches without sacrificing the active width of non-volatile semiconductor memory devices and the second spacer technique is used to highly adjust the coupling ratio of the self-aligned floating gate using shallow-trench-isolation, where the first polycrystalline-silicon spacers are formed on the sidewalls of the etched first masking silicon-nitride layer and the etched first polycrystalline-silicon layer after etching the planarized filling isolation oxides having an adjustable thickness t of the first masking silicon-nitride layer plus the thickness of the first polycrystalline-silicon layer. The first masking silicon-nitride layers are removed in a self-aligned manner and the dielectric layer is then formed on the patterned first polycrystalline-silicon layer, the formed first polycrystalline-silicon spacers and the etched filling isolation-oxides. The first dielectric layer can be a composite layer of silicon oxide-silicon nitride-silicon oxide (ONO) layer. A second polycrystalline-silicon layer and then a silicide layer are deposited to form the control gate. It is clearly seen that the coupling ratio of the self-aligned floating gate of the present invention is much increased as compared to that of the prior arts and the effective active layer width xcex is not affected by forming the channel stops of shallow-trench-isolation and oxidizing the surface of the etched trenches. Therefore, the effective active layer width per cell is only 2xcex, where xcex is the minimum-feature-size of technology used. The third spacer technique of the present invention uses the second silicon-oxide spacers formed on the sidewalls of the patterned and etched first masking polycrystalline-silicon layer to define the gate length xcex94L of stacked-gate flash memory devices and the second masking silicon-nitride layer is etched and is used as a hard mask to etch the silicide layer, the second polycrystalline-silicon layer , the first dielectric layer, the first polycrystalline-silicon spacers, and the first polycrystalline-silicon layer. The thermal oxidation is performed to grow thin first poly-oxide layers on the sidewalls of the etched first polycrystalline-silicon layer, the etched first polycrystalline-silicon spacer and the etched second polycrystalline-silicon layer. The implantation of arsenic impurities across the first thermal-oxide layer is performed in a self-aligned manner to form the mid-doped source/drain diffusion regions of stacked-gate flash memory devices. The fourth spacer technique of the present invention is performed to form the thin silicon-nitride spacers on the sidewalls of the stacked-gate structure for self-aligned heavily-doped source/drain implant, self-aligned source/drain or common buried-source silicidation, and self-aligned contacts. It is clearly seen that the effective length per cell is only xcex(1+xcex94L/xcex), which is much smaller than that of the prior arts in which the gate length of stacked-gate flash memory devices is based on the minimum feature size of technology used. For a NOR-type configuration with common buried-source, the effective cell size is only 2xcex2(1+xcex94L/xcex). It is clearly understood that xcex94L less than xcex can be easily implemented using existing spacer formation technique and the effective cell size can be made to be smaller than 4xcex2(for xcex94L=xcex) and is adjustable through the width of the spacer xcex94L. Moreover, since the gate length is smaller than the minimum feature size of technology used, the applied source-drain voltage for programming can be reduced and the applied control-gate voltage can be reduced accordingly due to the very high coupling ratio of the self-aligned floating gate of the present invention. Similarly, the applied erasing voltage across the control gate and the substrate can be also reduced. As consequence, a method of fabricating the scalable stacked-gate flash memory device of the present invention can be used to implement high-density, high-speed, low-voltage and low-power flash memory array and system for mass storage applications.